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| TEA6425 VIDEO CELLULAR MATRIX . . . . . . . . . 6 VIDEO INPUTS - 8 VIDEO OUTPUTS 2 INTERNAL SELECTABLE YC ADDERS 15MHz BANDWIDTH @ -3dB SELECTABLE 0.5/6.5dB GAIN FOR EACH OUTPUT HIGH IMPEDANCE SWITCH FOR EACH OUTPUT (3-state operation) PROGRAMMABLE CLAMP MODE ON EACH INPUT (sync bottom or average value) -60dB CROSSTALK @ 5MHz 4 SUB-ADDRESS CAPABILITY I2C BUS CONTROL DIP20 (Plastic Package) ORDER CODE : TEA6425 DESCRIPTION This device is intended for switching between video and chroma signals such as CVBS, SVHS, baseband CVBS, MAC. Each input clamp mode, each output gain, all switching are controlled through the I2C bus. The 8 outputscan be set separatelyin high impedance state, to enable parallel DC connection of several devices (up to 4). PIN CONNECTIONS SO20L (Plastic Micropackage) ORDER CODE : TEA6425D IN 1 SDA 1 20 V CC OUT 1 2 3 4 5 6 19 18 17 16 15 IN 2 SCL IN 3 IN 4 SUB OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 7 8 9 10 14 13 12 11 IN 5 V CCP IN 6 OUT 7 OUT 8 6425-01.EPS GND May 1996 1/9 TEA6425 BLOCK DIAGRAM 1 PRO G. CLAMP PRO G. CLAMP PRO G. CLAMP PRO G. CLAMP PRO G. CLAMP PRO G. CLAMP 3 5 INPUTS 6x8 MATRIX 6 8 10 S CL 4 I2C DECODER S DA 2 S UB-ADDRES S 7 VCC 1 9 0/6 dB 0/6 dB 0/6 dB 0/6 dB 0/6 dB 0/6 dB 0/6 dB 0/6 dB VCC 2 20 3 S TATE OUTPUTS 11 GND OUTP UTS 12 13 14 15 16 17 18 19 6425-02.EPS TEA6425 CELLULAR MATRICE CONNECTIONS 1st/4 addresses 2nd/4 addresses CVBS or C I2 C DECODER I2 C DECODER PROG. CLAMP 6 INPUTS ADDER 0dB 6dB 3 STATE OUT IC3 IC4 6425-03.EPS 8 OUTPUTS LINES 2/9 6 INPUTS 6X8 Full MATRIX IC1 6X8 Full MATRIX IC2 TEA6425 ABSOLUTE MAXIMUM RATINGS Symbol VCC VI Toper Tstg Supply Voltage Voltage at Pin i to GND Operating Ambient Temperature Storage Temperature Parameter Value 12 0, VCC 0, + 70 -20, + 150 Unit V V o o C C THERMAL DATA Symbol R th (j-a) Parameter Junction-ambient Thermal Resistance Min. Value 80 Unit o C/W ELECTRICAL CHARACTERISTICS (VCC = 8V, Tamb = 25oC, VIN = 1V, Gain = 6.5dB, Cload = 20pF, Rload = 4.7k ; Gain condition, clamp and 3-state are controlled by I2C bus, unless otherwise specified) Symbol SUPPLY VCC ICC RR VIN Vclamp VDC IIN Iclamp R OUT ZHI C HI G1 G2 Vsync Vbias Supply Voltage Supply Current Supply Voltage Rejection Max. Signal Amplitude Clamp Level Input DC Level Leakage Current Clamp Current Output Resistance Output "off" Impedance COUT in 3-state Voltage Gain Voltage Gain Top Level Sync (Y or CVBS) Output Mean Level (chroma) Isolation "off" State Crosstalk Attenuation between Channels Bandwidth 7.2 f = 1kHz Clamp Active Clamp Active Clamp Inactive 1 input connected to 1 output Vcla mp - 200mV 40 2 1.7 2.7 8 45 46 8.8 60 V mA dB VPP V V A mA k pF dB dB V V V dB dB MHz Parameter Test Conditions Min. Typ. Max. Unit VIDEO INPUTS (clamping at bottom sync level) 2 3 2 0.9 15 no load no load f = 100kHz f = 100kHz G = 6.5dB, Clamp Active G = 0.5dB, Clamp Inactive G = 6.5dB, Clamp Inactive f = 5MHz f = 5MHz C load = 20pF, G = 6.5dB at 0.5dB at 1dB at - 3dB 50 0 6 1 2 3 60 50 3 0.5 6.5 1.25 2.4 3.4 60 5 10 21 1 7 2 3 4 2.3 3.3 5 3 50 VIDEO OUTPUTS FUNCTIONAL DESCRIPTION This device is controlled via the I2C bus. 4 addresses can be selected by a 4-level detector on Pin 7, thus enabling parallel connection of 4 devices. Via the I2C bus : - The input signals can be clamped at their negative peak (top sync). - The gain factor of the outputs can be selected between 0.5 and 6.5dB. - Each of the 6 inputs can be connected to the 8 outputs. - Each output can individually be set in a high impedance state. Two internal SVHS mixers will add the selected Y and C inputs. Two dedicated outputs will have the option to select this added signal also. 3/9 6425-03.TBL B 6425-02.TBL 6425-01.TBL TEA6425 I2C BUS CHARACTERISTICS Symbol SCL VIL VIH ILI fSCL tR tF CI SDA VIL VIH ILI CI tR tF VOL tF CL TIMING tLOW tHIGH tSU, DAT tHD, DAT tSU, STO tBUF tHD, STA tSU, STA Clock Low Period Clock High Period Data Set-up Time Data Hold Time Set-up Time from Clock High to Stop Start Set-up Time following a Stop Start Hold Time Start Set-up Time following Clock Lowto High Transition 4.7 4.0 250 0 4.0 4.7 4.0 4.7 1.3 0.6 100 0 0.6 1.3 0.6 0.6 s s ns ns s s s s Low Level Input Voltage High Level Input Voltage Input Leakage Current Input Capacitance Input Rise Time Input Fall Time Low Level Output Voltage Output Fall Time Load Capacitance - 0.3 3.0 - 10 + 1.5 VCC + 0.5 + 10 10 1000 300 0.4 250 400 - 0.3 3.0 - 10 + 1.5 VCC + 0.5 + 10 10 300 300 0.4 250 400 V V A pF ns ns V ns pF Low Level Input Voltage High Level Input Voltage Input Leakage Current Clock Frequency Input Rise Time Input Fall Time Input Capacitance - 0.3 3.0 - 10 0 + 1.5 VCC + 0.5 + 10 100 1000 300 10 - 0.3 3.0 - 10 0 + 1.5 VCC + 0.5 + 10 400 300 300 10 V V A kHz ns ns pF Parameter Test Conditions Standard Mode Min. Max. Fast Mode Min. Max. Unit VI = 0 to VDD 1.5V to 3V 1.5V to 3V VI = 0 to VDD 1.5V to 3V 1.5V to 3V IOL = 3mA 3V to 1.5V 340 340 Figure 1 : I2C Bus Timing SDA t BUF t LOW tf SCL t HD,STA tr t HD,DAT t HIGH t SU,DAT SDA t SU,STA t SU,STO 6425-04.EPS 4/9 6425-04.TBL TEA6425 I2C BUS SELECTION I2C Bus Slave Address Address Value A6 1 A5 0 A4 0 A3 1 A2 0 A1 A1 A0 A0 R/W 0 Sub-address I2C Symbol Vsub Parameter Slave address HEXA Conditions Sub-address (see note) A1 A0 0 0 1 1 1 0 0 1 Pin 7 Voltage (typ.) Unit 1 2 3 4 90 96 94 92 GND VCC 1/3 2/3 V V VCC VCC Note : The first 3 levels are defined by connecting the sub-address pin to the appropriate level. Sub-address 4 will be selected when this pin is left open. 1st Data Byte b7 a2 0 0 0 0 1 1 1 1 b6 a1 0 0 1 1 0 0 1 1 b5 a0 0 1 0 1 0 1 0 1 b4 * * * * * * * * * b3 * * * * * * * * * b2 * * * * * * * * * b1 * * * * * * * * * b0 I 0 0 0 0 0 0 0 0 Selected Output OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 Output Select 2nd Data Byte b7 a2 0 0 0 0 1 1 * * * * * * * * b6 a1 0 0 1 1 0 0 * * * * * * * * b5 a0 0 1 0 1 0 1 * * * * * * * * b4 * * * * * * * 0 1 * * * * * * b3 * * * * * * * * * 0 1 * * * * b2 * * * * * * * * * * * 0 1 * * b1 * * * * * * * * * * * * * 0 1 b0 I 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Action IN1 IN2 IN3 IN4 IN5 IN6 Free Clamped 0.5dB 6.5dB Disabled Enabled Low impedance Tri-state Input Select Clamp Gain Mixer Tri-state Power On Reset When active : outputs in 3-state, inputs are clamped. Symbol Reset Parameter Start of Reset End of Reset Conditions Incr. VCC Decr. VCC Incr. VCC Min. Typ. Max. 2.5 4.2 Unit V V V 5/9 4.5 TEA6425 PIN CONFIGURATIONS Figure 2 : Video IN Clamp V REF VREF Clamp Pins 1 - 3 - 5 6 - 8 - 10 to Matrix 6425-05.EPS Figure 3 : Video OUT TRI-STATE TRI-STATE TRI-STATE Pins 12 - 13 - 14 - 15 16 - 17 - 18 - 19 From Matrix TRISTATE TRI-STATE TRISTATE TRISTATE V REF 6425-06.EPS TRISTATE Figure 4 : PROG Pin Figure 5 : Bus Inputs VC C VC C 20k ESD PROT. 7 40k VREF to CMOS Pins 2-4 V REF to CMOS X4 3 TIMES IN // 6425-07.EPS ACKN 6425-08.EPS For SDA only 6/9 TEA6425 TYPICAL APPLICATION VCC (+8V ) 22F 1 0H 75 Y C 220nF 220nF EXT SVHS OUT 75 4.7k 9 C1 Y1 1 C2 C1 3 4.7k 11 20 19 SVHS1 IN 2x 75 C3 5 C4 6 C5 Y2 8 SVHS2 IN C6 C2 10 T E A 6 4 2 5 2 4 7 TO PIP PROCESSOR (CVBS or Y+C) 4.7k 18 17 16 15 14 13 12 CVBS/Y C TO TV PROCESSOR (CVBS or YC) 2x 75 I2 C SDA SCL 2 4 7 TUNER OUT (CVBS) SCART 1 (CVBS IN) C7 1 C8 3 75 19 C9 SCART 2 (CVBS IN) C10 5 6 C11 SCART 3 (CVBS IN) 3x 75 8 C12 10 9 T E A 6 4 2 5 11 20 18 17 16 15 14 75 75 SCART 1 (CVBS OUT) SCART 2 (CVBS OUT) SCART 3 (CVBS OUT) 13 12 6x 4.7k 220nF Y COMB FILTER C 220nF (CVBS) SVHS 1/2 (Y+C) 4.7k 6425-09.EPS 7/9 TEA6425 PACKAGE MECHANICAL DATA 20 PINS - PLASTIC DIP Dimensions a1 B b b1 D E e e3 F I L Z Min. 0.254 1.39 Millimeters Typ. Max. 1.65 Min. 0.010 0.055 Inches Typ. Max. 0.065 0.45 0.25 25.4 8.5 2.54 22.86 7.1 3.93 3.3 1.34 0.018 0.010 1.000 0.335 0.100 0.900 0.280 0.155 0.130 0.053 DIP20.TBL 8/9 PM-DIP20.EPS TEA6425 PACKAGE MECHANICAL DATA 20 PINS - PLASTIC MICROPACKAGE Dimensions A a1 a2 b b1 C c1 D E e e3 F L M S Min. 0.1 0.35 0.23 Millimeters Typ. Max. 2.65 0.3 2.45 0.49 0.32 45 (typ.) o Min. 0.004 0.014 0.009 Inches Typ. Max. 0.104 0.012 0.096 0.019 0.013 0.5 12.6 10 1.27 11.43 7.4 0.5 7.6 1.27 0.75 8o (Max.) 0.291 0.020 13.0 10.65 0.496 0.394 0.020 0.512 0.419 0.050 0.450 0.299 0.050 0.030 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1996 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of I2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 9/9 SO20.TBL PM-SO20.EPS |
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